Author of the publication

Integrating security constraints into fixed priority real-time schedulers.

, , , and . Real Time Syst., 52 (5): 644-674 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems., and . IEEE Trans. Computers, 59 (3): 400-415 (2010)A composable worst case latency analysis for multi-rank DRAM devices under open row policy., , and . Real Time Syst., 52 (6): 761-807 (2016)Real-Time Computing on Multicore Processors., , , , , , , , , and 1 other author(s). Computer, 49 (9): 69-77 (2016)Global Real-Time Memory-Centric Scheduling for Multicore Systems., , , , and . IEEE Trans. Computers, 65 (9): 2739-2751 (2016)HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs., , , and . FPGA, page 222-231. ACM, (2019)A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources., , , , and . ECRTS, volume 262 of LIPIcs, page 17:1-17:25. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)A Requests Bundling DRAM Controller for Mixed-Criticality Systems., and . RTAS, page 247-258. IEEE Computer Society, (2017)Memory Servers for Multicore Systems., and . RTAS, page 97-108. IEEE Computer Society, (2016)A design-space exploration for allocating security tasks in multicore real-time systems., , , and . DATE, page 225-230. IEEE, (2018)ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs., , , and . ICECCS, page 11-22. IEEE Computer Society, (2009)