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Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.

S. Zhang, X. Li, R. Blanton, J. da Silva, J. Jr., and K. Butler. ITC, page 1-10. IEEE Computer Society, (2014)

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Marco Jose Da Silva

Tiago Jose da Silva Lopes

Celson José Silva

Alexandre José Silva

António José Silva

Other publications of authors with the same name

An Approach to Testability Improvement of Mixed-Signal Boards.J. Matos, J. Ferreira, A. Leão, and J. da Silva. ISCAS, page 161-164. IEEE, (1994)Biot-Granier Sensor: A Novel Strategy to Measuring Sap Flow in Trees.J. Siqueira, T. Paço, J. da Silva, and J. Silvestre. Sensors, 20 (12): 3538 (2020)Design for Calibratability of a N-Integer Low-Frequency Phase-Locked Loop.R. Teixeira, and J. da Silva. DCIS, page 1-6. IEEE, (2018)Architecture of test support ICs for mixed-signal testing.J. Matos, J. Ferreira, A. Leão, and J. da Silva. VTS, page 240-246. IEEE Computer Society, (1994)Mixed-Signal BIST Using Correlation and Reconfigurable Hardware.J. da Silva, J. Duarte, and J. Matos. DATE, page 744. IEEE Computer Society / ACM, (2000)An Active Implant to Restore Dental Proprioceptivity.J. da Silva, I. Cerrone, D. Malagón, J. Marinho, S. Mundy, J. Gaspar, and J. Mendes. DSD, page 316-319. IEEE, (2020)Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop.B. Kaminska, M. Lubaszewski, and J. da Silva. VLSI Design, (2008)An Alternative SNR Computation Method for ADC Testing.J. da Silva, and J. Alves. DCIS, page 1-6. IEEE, (2019)Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits.J. da Silva, J. Matos, I. Bell, and G. Taylor. J. Electron. Test., 9 (1-2): 75-88 (1996)Special issue of Microelectronics Journal on the Conference on Design of Circuits and Integrated Systems 2011 (DCIS 2011).J. da Silva, S. Renaud, and J. Ferreira. Microelectron. J., 44 (10): 869 (2013)

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Disambiguation of "da Silva, José Machado"

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Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.

Please choose a person to relate this publication to

Marco Jose Da Silva

Tiago Jose da Silva Lopes

Celson José Silva

Alexandre José Silva

António José Silva

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "da Silva, José Machado"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.

Please choose a person to relate this publication to

Marco Jose Da Silva

Tiago Jose da Silva Lopes

Celson José Silva

Alexandre José Silva

António José Silva

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling.