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A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller., , , , , , , , , and 1 other author(s). IEEE Real Time Technology and Applications Symposium, page 210-219. IEEE Computer Society, (1998)Instruction fetch and dispatch scheme with flag-in-cache/in-IBR., , , , , and . Syst. Comput. Jpn., 29 (4): 86-94 (1998)3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor., , , , , , , and . IEEE J. Solid State Circuits, 29 (3): 298-302 (March 1994)2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor., , , , , , , , and . IEEE J. Solid State Circuits, 31 (7): 972-980 (1996)A 120-MHz BiCMOS superscalar RISC processor., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 29 (4): 389-396 (April 1994)A high performance BiCMOS 32-bit microprocessor., , , , , , , , , and 1 other author(s). ICCD, page 358-361. IEEE, (1989)A superscalar RISC processor with pseudo vector processing feature., , , , , , , and . ICCD, page 102-109. IEEE Computer Society, (1995)A 13.3ns double-precision floating-point ALU and multiplier., , , , , and . ICCD, page 466-470. IEEE Computer Society, (1995)