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Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, C. Lin, J. Wu, C. Shuai, S. Wu, J. Myers, K. Doppler, M. Fujita, and S. Yamazaki. VLSI Circuits, page 1-2. IEEE, (2016)

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Y Winter

Y Mardiyati

Y LeConte

Rainer Y

Lou Y

Other publications of authors with the same name

Muon (g-2) Technical Design ReportJ. Grange, V. Guarino, P. Winter, K. Wood, H. Zhao, R. Carey, D. Gastler, E. Hazen, N. Kinnaird, J. Miller and 193 other author(s). (Jan 27, 2015)Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, C. Lin, J. Wu and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Design of X-band complementary metal-oxide semiconductor-based frequency-modulation continuous-wave sensor.C. Chang, S. Wang, H. Wu, E. Liang, A. Liu, K. Tsai, M. Chiang, P. Yang, Y. Wu, H. Lee and 1 other author(s). IET Circuits Devices Syst., 3 (6): 331-339 (2009)Spiral waves in disinhibited mammalian neocortexX. Huang, W. Troy, Q. Yang, H. Ma, C. Laing, S. Schiff, and J. Wu. J.~Neurosci., 24 (44): 9897--9902 (2004)Dynamical evolution of spatiotemporal patterns in mammalian middle cortexS. Schiff, X. Huang, and J. Wu. Phys.~Rev.~Lett., (2007)Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, J. Wu, C. Shuai, S. Wu and 4 other author(s). IEEE J. Solid State Circuits, 52 (4): 925-932 (2017)Odoo ERP with Business Intelligence Tool for a Small-Medium Enterprise: A Scenario Case Study.J. Wu, and L. Chen. IC4E, page 323-327. ACM, (2020)Symmetric Schröder paths and restricted involutions.E. Deng, M. Dukes, T. Mansour, and S. Wu. Discret. Math., 309 (12): 4108-4115 (2009)Linked partitions and linked cycles.W. Chen, S. Wu, and C. Yan. Eur. J. Comb., 29 (6): 1408-1426 (2008)

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Disambiguation of "Wu, J. Y."

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Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

Please choose a person to relate this publication to

Y Winter

Y Mardiyati

Y LeConte

Rainer Y

Lou Y

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wu, J. Y."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.

Please choose a person to relate this publication to

Y Winter

Y Mardiyati

Y LeConte

Rainer Y

Lou Y

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.