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Using Novel Configuration Techniques for Accelerated FPGA Aging., , , , , and . FPL, page 169-175. IEEE, (2020)Designing and Debugging Custom Computing Applications., , and . IEEE Des. Test Comput., 17 (1): 20-28 (2000)New approaches for in-system debug of behaviorally-synthesized FPGA circuits., and . FPL, page 1-6. IEEE, (2014)Comparing fine-grained performance on the Ambric MPPA against an FPGA., , , and . FPL, page 174-179. IEEE, (2009)Using Physical and Functional Comparisons to Assure 3rd-Party IP for Modern FPGAs., , , and . IVSW, page 80-86. IEEE, (2018)Distributed-Memory Based FPGA Debug: Design Timing Impact., and . FPT, page 350-353. IEEE, (2018)Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification., , , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 483-492. Springer, (2001)The flexibility of configurable computing., and . IEEE Signal Process. Mag., 15 (5): 67-84 (1998)Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs., and . VLSI Signal Processing, 12 (1): 67-86 (1996)Synthesizing RTL Hardware from Java Byte Codes., , and . FPL, volume 2147 of Lecture Notes in Computer Science, page 123-132. Springer, (2001)