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Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA., , , , , and . IEEE Access, (2020)Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators., , , , , , , and . IEEE Embed. Syst. Lett., 11 (3): 69-72 (2019)Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy., , , and . J. Signal Process. Syst., 87 (1): 81-106 (2017)Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing., and . J. Signal Process. Syst., 91 (7): 701-702 (2019)A Dataflow Implementation of Inverse Kinematics on Reconfigurable Heterogeneous MPSoC., , , , , and . CPS Summer School, PhD Workshop, volume 2457 of CEUR Workshop Proceedings, page 107-118. CEUR-WS.org, (2019)Optimization and deployment of CNNs at the edge: the ALOHA experience., , , , , , , , , and 8 other author(s). CF, page 326-332. ACM, (2019)CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of reconfigurable systems in unceRtain hybRid envirOnments: Invited paper: CERBERO teams from UniSS, UniCA, IBM Research, TASE, INSA-Rennes, UPM, USI, Abinsula, AmbieSense, TNO, S&T, CRF., , , , , , , , , and 11 other author(s). CF, page 320-325. ACM, (2019)Towards self-adaptive networks on chip for massively parallel processors: multilevel quality of service programmability., , , and . Conf. Computing Frontiers, page 19. ACM, (2011)Dataflow-Based Design of Coarse-Grained Reconfigurable Platforms., , , , and . SiPS, page 127-129. IEEE, (2016)Elicitation of technical requirements in large research projects: the CERBERO approach., , , , , , and . SAC, page 1629-1632. ACM, (2019)