( en | de | ru )

 

Disambiguation of "Mehendale, Mahesh"

Author of the publication

copydeleteadd this publication to your clipboard
FDT-a design tool for switched capacitor filters.

, , , , , and . ICCAD, page 446-449. IEEE Computer Society, (1989)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mahesh Darna

Mahesh Kandasamy

Mahesh Sooriyabandara

Mahesh Darna

Mahesh Darna

 

Other publications of authors with the same name

Low-power realization of FIR filters on programmable DSPs., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (4): 546-553 (1998)RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge., , , , , , and . CoRR, (2023)Integrated IC design approach based on software engineering paradigm., and . CICC, page 53-56. IEEE, (1999)Challenges in the Design of Embedded Real-time DSP SoCs.. VLSI Design, page 507-511. IEEE Computer Society, (2004)Multivoltage scheduling with voltage-partitioned variable storage., , and . ISLPED, page 298-301. ACM, (2003)Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth., , , and . MICRO, page 38-50. IEEE Computer Society, (2014)FDT-a design tool for switched capacitor filters., , , , , and . ICCAD, page 446-449. IEEE Computer Society, (1989)Session 4 overview: Digital processors., and . ISSCC, page 70-71. IEEE, (2016)Improving performance of high precision signal processing algorithms on programmable DSPs., and . ISCAS (3), page 488-491. IEEE, (1999)Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities., , , and . ICS, page 257-266. ACM, (2012)