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DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback., and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (7): 530-534 (2009)A continuous time ΔΣ modulator with reduced clock jitter sensitivity through DSCR feedback., , , and . NORCHIP, page 1-4. IEEE, (2011)A low-power 2nd-order CT ΔΣ modulator with an asynchronous SAR quantizer., , , and . NORCHIP, page 1-4. IEEE, (2014)Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1659-1668 (2013)A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current., and . ESSCIRC, page 240-243. IEEE, (2007)A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation., , , , , , , , , and 1 other author(s). ISSCC, page 336-337. IEEE, (2013)Design of a Configurable Complex IF Receiver Supporting LTE Carrier Aggregation., , , , , and . VTC Spring, page 1-5. IEEE, (2013)A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS., , , , , , , , , and . ESSCIRC, page 470-473. IEEE, (2012)A Filtering ΔΣ ADC for LTE and Beyond., , , , and . IEEE J. Solid State Circuits, 49 (7): 1535-1547 (2014)A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology., , , , , , , , , and 8 other author(s). ESSCIRC, page 237-240. IEEE, (2022)