Author of the publication

An Interconnect Channel Design Methodology for High Performance Integrated Circuits.

, , , and . DATE, page 1138-1143. IEEE Computer Society, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

An RRAM-based Oscillatory Neural Network., , , , and . LASCAS, page 1-4. IEEE, (2015)Efficient per-nonlinearity distortion analysis for analog and RF circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (10): 1297-1309 (2003)Asymptotic Probability Extraction for Nonnormal Performance Distributions., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (1): 16-37 (2007)Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (6): 1041-1054 (2008)Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (2): 210-215 (1997)Equipotential shells for efficient inductance extraction., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (1): 70-79 (2001)Global and local congestion optimization in technology mapping., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 498-505 (2003)Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation., , and . VLSI Design, 15 (3): 605-618 (2002)Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 623-637 (2009)Securing Digital Systems via Split-Chip Obfuscation., , and . CoRR, (2020)