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Disambiguation of "Beukema, Troy J."

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3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI.

, , , , , , , , , , and . ISSCC, page 56-57. IEEE, (2016)

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Stefanie Troy

Peter Troyke

Troy Wilson

Alfonso Luís Troya Chinchilla

Maria Troyer

 

Other publications of authors with the same name

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 41 (12): 2885-2900 (2006)A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (4): 897-910 (2012)A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications., , , , , , , and . IEEE J. Solid State Circuits, 41 (12): 2820-2831 (2006)A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2012)A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 213-222. IEEE, (2006)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers., , and . CICC, page 639-642. IEEE, (2007)Design considerations for high-data-rate chip interconnect systems.. IEEE Communications Magazine, 48 (10): 174-183 (2010)A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (12): 2633-2645 (2005)Developing integrated antenna subsystems for laptop computers., , , , , and . IBM J. Res. Dev., 47 (2-3): 355-367 (2003)