Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.

F. Tu, S. Yin, P. Ouyang, S. Tang, L. Liu, and S. Wei. IEEE Trans. Very Large Scale Integr. Syst., 25 (8): 2220-2233 (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shaojun Lu

Shaojun Tong

Wei Wei

Other publications of authors with the same name

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation.J. Gu, S. Yin, L. Liu, and S. Wei. ASP-DAC, page 312-317. IEEE, (2017)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.S. Tang, S. Yin, S. Zheng, P. Ouyang, F. Tu, L. Yao, J. Wu, W. Cheng, L. Liu, and S. Wei. NVMSA, page 1-6. IEEE, (2017)Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.H. Luo, S. Wei, D. Chen, and D. Guo. J. Parallel Distributed Comput., 74 (9): 2818-2830 (2014)Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system.L. Liu, Y. Chen, S. Yin, L. Zhou, H. Yuan, and S. Wei. Sci. China Inf. Sci., 57 (8): 1-14 (2014)Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.Y. Wang, L. Liu, S. Yin, M. Zhu, P. Cao, J. Yang, and S. Wei. Sci. China Inf. Sci., 56 (11): 1-20 (2013)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems.G. Peng, L. Liu, Q. Wei, Y. Wang, S. Yin, and S. Wei. A-SSCC, page 191-194. IEEE, (2018)Polyhedral model based mapping optimization of loop nests for CGRAs.D. Liu, S. Yin, L. Liu, and S. Wei. DAC, page 19:1-19:8. ACM, (2013)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays.C. Yang, L. Liu, S. Yin, and S. Wei. DAC, page 64:1-64:6. ACM, (2016)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference.S. Zheng, Y. Liu, S. Yin, L. Liu, and S. Wei. DAC, page 137:1-137:6. ACM, (2018)LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA.X. Lin, S. Yin, F. Tu, L. Liu, X. Li, and S. Wei. DAC, page 16:1-16:6. ACM, (2018)

BibSonomy

Disambiguation of "Wei, Shaojun"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wei, Shaojun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.

Please choose a person to relate this publication to

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.