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VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms., , , , and . PATMOS, page 1-8. IEEE, (2014)Approximating a Multi-Grid Solver., , , and . PMBS@SC, page 97-107. IEEE, (2018)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)Architectural support for efficient message passing on shared memory multi-cores., , , and . J. Parallel Distributed Comput., (2016)Hardware Versus Software Fault Injection of Modern Undervolted SRAMs., , , , , and . CoRR, (2019)Exceeding Conservative Limits: A Consolidated Analysis on Modern Hardware Margins., , , , , , , and . CoRR, (2020)System-level power-aware design techniques in real-time systems., and . Proc. IEEE, 91 (7): 1055-1069 (2003)Efficient selective replication of critical code regions for SDC mitigation leveraging redundant multithreading., and . J. Supercomput., 77 (12): 14130-14160 (2021)Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications., , , , , , , , , and 14 other author(s). ACM Trans. Archit. Code Optim., 20 (2): 28:1-28:25 (June 2023)Profile-guided transaction coalescing - lowering transactional overheads by merging transactions., , , , and . ACM Trans. Archit. Code Optim., 10 (4): 50:1-50:18 (2013)