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Disambiguation of "Iwasaki, Kazuhiko"

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Analysis of Read and Write Availability for Generalized Hybrid Data Replication Protocol.

, , , , , and . PRDC, page 143-150. IEEE Computer Society, (2004)

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Kazuhiko Yoshida

Kazuhiko Yoshida

Kazuhiko Sano

Kazuhiko Uzawa

Kazuhiko Yoshida

 

Other publications of authors with the same name

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers., , , and . IEEE Trans. Computers, 44 (11): 1265-1274 (1995)Reduction of Area per Good Die for SoC Memory Built-In Self-Test., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2463-2471 (2010)Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test., , , , and . J. Low Power Electron., 5 (4): 520-528 (2009)Analysis of Fault Detection Probability of CMOS Combinational Circuits and Its Application to Signature Testing.. Syst. Comput. Jpn., 21 (5): 29-38 (1990)Aliasing Probabilities and Weight Distributions of Several Codes., and . Syst. Comput. Jpn., 20 (9): 81-88 (1989)Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters., , , , and . Asian Test Symposium, page 190-195. IEEE Computer Society, (2004)Note on Layout-Aware Weighted Probabilistic Bridge Fault Coverage., , and . Asian Test Symposium, page 89-94. IEEE Computer Society, (2012)Analysis of Probabilistic Trapezoid Protocol for Data Replication., , , , and . DSN, page 782-791. IEEE Computer Society, (2005)Aliasing Error for a Mask ROM Built-In Self-Test., and . IEEE Trans. Computers, 45 (3): 270-277 (1996)Application of Partially Rotational Scan Technique with Tester IP for Processor Circuits., , , , and . IEICE Trans. Inf. Syst., 87-D (3): 586-591 (2004)