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Customizing and hardwiring on-chip interconnects in FPGAs.

. Delft University of Technology, Netherlands, (2011)base-search.net (fttudelft:oai:tudelft.nl:uuid:894e4234-ed2b-411f-be90-550766f97cd5).

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Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 49-60. Springer, (2007)Representing Contiguity in Page Table for Memory Management Units.. MCSoC, page 21-28. IEEE Computer Society, (2017)Customizing and hardwiring on-chip interconnects in FPGAs.. Delft University of Technology, Netherlands, (2011)base-search.net (fttudelft:oai:tudelft.nl:uuid:894e4234-ed2b-411f-be90-550766f97cd5).Near-Threshold L1 Data Cache for Yield Management Under Process Variations., and . IEEE Access, (2020)Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays., , , and . IET Comput. Digit. Tech., 6 (6): 396-405 (2012)Design Trade-offs in Customized On-chip Crossbar Schedulers., , and . J. Signal Process. Syst., 58 (1): 69-85 (2010)TLC STT-MRAM aware LLC for multicore processor., , and . IEICE Electron. Express, 17 (24): 20200359 (2020)Block Level TLB Coalescing for Buddy Memory Allocator.. IEICE Trans. Inf. Syst., 102-D (10): 2043-2046 (2019)Virtual Address Remapping with Configurable Tiles in Image Processing Applications.. IEICE Trans. Inf. Syst., 103-D (2): 309-320 (2020)Customisation of on-chip network interconnects and experiments in field-programmable gate arrays., , , and . IET Comput. Digit. Tech., 6 (1): 59-68 (2012)