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A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC., , , , , and . ISSCC, page 184-595. IEEE, (2007)A 32 Gb/s Rx only equalization transceiver with 1-tap speculative FIR and 2-tap direct IIR DFE., , , and . VLSI Circuits, page 1-2. IEEE, (2016)An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications., , , and . APCCAS, page 500-503. IEEE, (2010)A 5-Bit 500-MS/S Flash ADC using Time-Domain Comparison., , , , and . Journal of Circuits, Systems, and Computers, (2012)A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process., , , , and . ASP-DAC, page 89-90. IEEE, (2013)Effect of Providing a Web-Based Collaboration Medium for Remote Customer Troubleshooting Tasks., , , and . HCI (9), volume 4558 of Lecture Notes in Computer Science, page 47-53. Springer, (2007)Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces., and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 701-711 (2014)A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1461-1469 (2009)An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (10): 2156-2163 (2014)A New Energy x Delay-Aware Flip-Flop., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (6): 1552-1557 (2006)