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A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection.

, , , , , and . ESSCIRC, page 225-228. IEEE, (2015)

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Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators., , , , , , , and . CICC, page 527-530. IEEE, (2004)A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS., , , , and . ISSCC, page 250-600. IEEE, (2007)A multimode CT ΔΣ-modulator with a reconfigurable digital feedback filter for semi-digital blocker/interferer rejection., , , , , and . ESSCIRC, page 225-228. IEEE, (2015)Modelling and optimization of low pass continuous-time sigma delta modulators for clock jitter noise reduction., , , and . ISCAS (1), page 1072-1075. IEEE, (2004)Design of Cascaded Continuous-Time Sigma-Delta Modulators., , , , , , and . ICECS, page 50-53. IEEE, (2006)A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution., , , , , and . IEEE J. Solid State Circuits, 39 (7): 1056-1063 (2004)A 15 MHz bandwidth sigma-delta ADC with 11 bits of resolution in 0.13μm CMOS., , , , , and . ESSCIRC, page 233-236. IEEE, (2003)10-bit, 3 mW continuous-time sigma-delta ADC for UMTS in a 0.12 μm CMOS process., , , , and . ESSCIRC, page 245-248. IEEE, (2003)A 10-bit, 4 mW continuous-time sigma-delta ADC for UMTS in a 0.12µm CMOS process., , and . ISCAS (1), page 1057-1060. IEEE, (2003)Common mode stability in fully differential voltage feedback CMOS amplifiers., , , and . ICECS, page 288-291. IEEE, (2003)