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A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.

, , , , , and . FPL, page 335-340. IEEE, (2005)

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Field-programmable logic and application : reconfigurable computing is going mainstream : 12th international conference, FPL 2002, Montpellier, France, September 2-4, 2002 : proceedings, , , , and . Springer, (2002)Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (3): 614-627 (2022)Selected Papers from ReCoSoC 2008., , , and . Int. J. Reconfigurable Comput., (2009)Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays.. IEEE Trans. Very Large Scale Integr. Syst., 16 (2): 134-143 (2008)Optimal Single Constant Multiplication Using Ternary Adders., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 928-932 (2018)A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks., , and . FPT, page 313-316. IEEE, (2007)A scalable reconfiguration mechanism for fast dynamic reconfiguration., , and . FPT, page 145-152. IEEE, (2008)More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers., , , , , and . ISCAS, page 1-5. IEEE, (2023)Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing., , , , , , , and . Conf. Computing Frontiers, page 404-418. ACM, (2004)Reconfigurable platforms for ubiquitous computing., , , , , , , and . Conf. Computing Frontiers, page 377-389. ACM, (2004)