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A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.

, , , , , and . FPL, page 335-340. IEEE, (2005)

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Evaluation of state-of-the-art neural network customized hardware., and . Neurocomputing, 2 (5): 209-231 (1990)Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters., , , , and . VLSI-SoC, page 302-307. IEEE, (2006)Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems., , , , and . IEEE International Workshop on Rapid System Prototyping, page 172-178. IEEE Computer Society, (2003)Prototyping of a High Performance Generic Viterbi Decoder., , , and . IEEE International Workshop on Rapid System Prototyping, page 42-47. IEEE Computer Society, (2002)Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing., , , , , , , and . Conf. Computing Frontiers, page 404-418. ACM, (2004)Reconfigurable platforms for ubiquitous computing., , , , , , , and . Conf. Computing Frontiers, page 377-389. ACM, (2004)PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels., , , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 219-228. Springer, (2008)Moment-Based Estimation of Switching Activity for Correlated Distributions., , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 859-868. Springer, (2004)On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects., , , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 819-828. Springer, (2004)Fuzzy neural networks: between functional equivalence and applicability., and . Int. J. Neural Syst., 6 (2): 185-196 (1995)