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Disambiguation of "Purnaprajna, Madhura"

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Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

, , , , , , , , , and . ACM Trans. Embedded Comput. Syst., 14 (2): 33:1--33:23 (2015)
DOI: 10.1145/2656207

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Madhura Purnaprajna

Madhura Purnaprajna

Madhura Purnaprajna

Madhura Purnaprajna

Madhura Purnaprajna

 

Other publications of authors with the same name

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs, , , , , , , , , and . ACM Trans. Embedded Comput. Syst., 14 (2): 33:1--33:23 (2015)Enabling seamless execution on hybrid CPU/FPGA systems: Challenges & directions., , and . FPL, page 1-8. IEEE, (2015)TileNET: Hardware accelerator for ternary Convolutional Neural Networks., , , , , and . Microprocess. Microsystems, (2021)k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational Genomics., , , and . VLSID, page 347-352. IEEE, (2019)MAPPARAT: A Resource Constrained FPGA-Based Accelerator for Sparse-Dense Matrix Multiplication., , , , and . VLSID, page 102-107. IEEE, (2022)Pushing the Limits of Energy Efficiency for Non-Binary LDPC Decoders on GPUs and FPGAs., , , , , , , , and . SiPS, page 1-6. IEEE, (2020)Recurrent Neural Networks: An Embedded Computing Perspective., , , and . IEEE Access, (2020)Demystifying Compression Techniques in CNNs: CPU, GPU and FPGA cross-platform analysis., , , , and . VLSID, page 240-245. IEEE, (2021)Gbit/s Non-Binary LDPC Decoders: High-Throughput using High-Level Specifications., , , , , and . FCCM, page 226. IEEE, (2020)Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case, , , , , , , , and . 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012, 29 April - 1 May 2012, Toronto, Ontario, Canada, page 224--231. (2012)