Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Recursive circuit clustering for minimum delay and area., and . FPGA, page 242. ACM, (2003)Constrained clock shifting for field programmable gate arrays., and . FPGA, page 121-126. ACM, (2002)FPGA and CPLD Architectures: A Tutorial., and . IEEE Des. Test Comput., 13 (2): 42-57 (1996)Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2331-2340 (2006)An area-efficient timing closure technique for FPGAs using Shannon's expansion., and . Integr., 40 (2): 167-173 (2007)Two-stage physical synthesis for FPGAs., , and . CICC, page 171-178. IEEE, (2005)From C to Blokus Duo with LegUp high-level synthesis., , , , , , , , , and 2 other author(s). FPT, page 486-489. IEEE, (2013)Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware., , and . FPT, page 152-159. IEEE, (2015)Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 232-241. Springer, (2002)The NUMAchine Multiprocessor., , , , , , , , , and 8 other author(s). ICPP, page 487-496. IEEE Computer Society, (2000)