Author of the publication

Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.

, , , , and . J. Electron. Test., 20 (4): 333-344 (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

The LRD traffic impact on the NoC-based SoCs., , , and . SBCCI, page 97-102. ACM, (2010)Burst-Mode Asynchronous Controllers on FPGA., , and . Int. J. Reconfigurable Comput., (2008)Functional verification of complete sequential behaviors: A formal treatment of discrepancies between system-level and RTL descriptions., , and . IDT, page 1-6. IEEE, (2013)On the Choice of Models of Computation for Writing Executable Specifications of System Level Designs., and . SBCCI, page 159-164. IEEE Computer Society, (2000)Formally verifying an RTOS scheduling monitor IP core in embedded systems., , , and . LATW, page 1-6. IEEE, (2011)BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units., , , and . LATW, page 64-69. IEEE, (2002)A PD-based methodology to enhance efficiency in testbenches with random stimulation., , and . SBCCI, ACM, (2009)Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection., , , and . Trans. Comput. Sci., (2010)Hybrid-on-chip communication architecture for dynamic MP-SoC protection., , , , and . SBCCI, page 1-6. IEEE, (2012)Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection., , , , and . SBCCI, page 1-6. IEEE, (2013)