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POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics.

, , , and . PACT, page 433-434. ACM, (2016)

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Analysing software prefetching opportunities in hardware transactional memory., , , , , , and . J. Supercomput., 78 (1): 919-944 (2022)Wrong-Path-Aware Entangling Instruction Prefetcher., and . IEEE Trans. Computers, 73 (2): 548-559 (February 2024)Speculative inter-thread store-to-load forwarding in SMT architectures., , , and . J. Parallel Distributed Comput., (March 2023)Compiler-Assisted Compaction/Restoration of SIMD Instructions., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs., , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 254-265. Springer, (2014)Exploring Instruction Fusion Opportunities in General Purpose Processors., , , and . MICRO, page 199-212. IEEE, (2022)Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors., , , , and . ICPP, page 562-571. IEEE Computer Society, (2013)Complexity-effective multicore coherence., and . PACT, page 241-252. ACM, (2012)PS-cache: An energy-efficient cache design for chip multiprocessors., , , and . PACT, page 407. IEEE Computer Society, (2013)An efficient cache design for scalable glueless shared-memory multiprocessors., , and . Conf. Computing Frontiers, page 321-330. ACM, (2006)