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Disambiguation of "Nakano, Masaya"

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A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.

, , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 213-221 (2016)

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Tomoyo Nakano

Hiroshi Daniel Nakano

 

Other publications of authors with the same name

A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm2 Density With Charge-Assisted Offset Cancellation Sense Amplifier., , , , , , , , , and . IEEE J. Solid State Circuits, 57 (10): 3094-3102 (2022)Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories., , , , , , , and . IEICE Trans. Electron., 88-C (2): 255-263 (2005)7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C., , , , , , , and . IEEE J. Solid State Circuits, 51 (1): 213-221 (2016)A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive., , , , , , , , , and . VLSI Circuits, page 210-. IEEE, (2019)A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier., , , , , , , , , and 5 other author(s). A-SSCC, page 1-3. IEEE, (2021)