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Layout optimizations to decrease internal power and area in digital CMOS standard cells.

J. Innocenti, F. Julien, J. Portal, L. Lopez, Q. Hubert, P. Masson, J. Sonzogni, S. Niel, and A. Régnier. MIPRO, page 1582-1587. IEEE, (2015)

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Gerhard Niel

Egid Niël

Luis Niel

Josef Niel

Fabien Niel

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A Schmitt trigger to benchmark the performance of a new zero-cost transistor.P. Devoge, H. Aziza, P. Lorenzini, P. Masson, A. Malherbe, F. Julien, A. Marzaki, A. Régnier, and S. Niel. ICECS 2022, page 1-4. IEEE, (2022)Dynamic current reduction of CMOS digital circuits through design and process optimization.J. Innocenti, L. Welter, N. Borrel, F. Julien, J. Portal, J. Sonzogni, L. Lopez, P. Masson, S. Niel, P. Dreux and 1 other author(s). PATMOS, page 77-81. IEEE, (2015)Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.J. Innocenti, L. Welter, F. Julien, L. Lopez, J. Sonzogni, S. Niel, A. Régnier, E. Paire, K. Labory, E. Denis and 2 other author(s). MWSCAS, page 897-900. IEEE, (2014)40nm SONOS Embedded Select in Trench Memory.R. Habhab, V. Marca, P. Masson, N. Miridi, C. Pribat, S. Jeannot, T. Kempf, M. Mantelli, P. Lorenzini, J. Voisin and 3 other author(s). ESSDERC, page 21-24. IEEE, (2023)Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology.P. Devoge, H. Aziza, P. Lorenzini, F. Julien, A. Marzaki, A. Malherbe, M. Mantelli, T. Sardin, S. Haendler, A. Régnier and 1 other author(s). DTIS, page 1-5. IEEE, (2021)Hot Electron Source Side Injection Comprehension in 40nm eSTM™.F. Melul, T. Kempf, V. Marca, M. Bocquet, M. Akbal, F. Trenteseaux, M. Mantelli, A. Régnier, S. Niel, and F. Rosa. IMW, page 1-4. IEEE, (2021)Benchmarking and optimization of trench-based multi-gate transistors in a 40 nm non-volatile memory technology.R. Gay, V. Marca, H. Aziza, A. Régnier, S. Niel, and A. Marzaki. DTIS, page 1-4. IEEE, (2021)Layout optimizations to decrease internal power and area in digital CMOS standard cells.J. Innocenti, F. Julien, J. Portal, L. Lopez, Q. Hubert, P. Masson, J. Sonzogni, S. Niel, and A. Régnier. MIPRO, page 1582-1587. IEEE, (2015)Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip.T. Kempf, V. Marca, L. Baron, F. Maugain, F. Rosa, S. Niel, A. Régnier, J. Portal, and P. Masson. IRPS, page 6. IEEE, (2018)Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor.P. Devoge, H. Aziza, P. Lorenzini, A. Malherbe, F. Julien, A. Marzaki, A. Régnier, and S. Niel. ISCAS, page 761-764. IEEE, (2022)

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Disambiguation of "Niel, Stephan"

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Layout optimizations to decrease internal power and area in digital CMOS standard cells.

Please choose a person to relate this publication to

Gerhard Niel

Egid Niël

Luis Niel

Josef Niel

Fabien Niel

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Niel, Stephan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Layout optimizations to decrease internal power and area in digital CMOS standard cells.

Please choose a person to relate this publication to

Gerhard Niel

Egid Niël

Luis Niel

Josef Niel

Fabien Niel

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Layout optimizations to decrease internal power and area in digital CMOS standard cells.