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Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability., , , and . Microelectron. Reliab., 47 (4-5): 559-566 (2007)Using dedicated device arrays for the characterization of TDDB in a scaled HK/MG technology., , , , , and . IRPS, page 1-6. IEEE, (2023)Combining SILC and BD statistics for low-voltage lifetime projection in HK/MG stacks., , , , and . IRPS, page 27-1. IEEE, (2022)Distribution and generation of traps in SiO2/Al2O3 gate stacks., , , , , and . Microelectron. Reliab., 47 (4-5): 525-527 (2007)Study of breakdown in STT-MRAM using ramped voltage stress and all-in-one maximum likelihood fit., , , , , , and . ESSDERC, page 146-149. IEEE, (2018)A new method for the analysis of high-resolution SILC data., , , , , , , , , and . Microelectron. Reliab., 43 (9-11): 1483-1488 (2003)Analysis and modeling of a digital CMOS circuit operation and reliability after gate oxide breakdown: a case study., , , , , and . Microelectron. Reliab., 42 (4-5): 555-564 (2002)A multi-bit/cell PUF using analog breakdown positions in CMOS., , , , , , , and . IRPS, page 2-1. IEEE, (2018)Engineering of a TiN\Al2O3\(Hf, Al)O2\Ta2O5\Hf RRAM cell for fast operation at low current., , , , , , and . ESSDERC, page 262-265. IEEE, (2015)A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (10): 2765-2776 (2019)