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Disambiguation of "Wey, I-Chyn"

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A 3.3 V 1 GHz high speed pipelined Booth multiplier.

, and . ISCAS (1), page 457-460. IEEE, (2002)

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Michael Wey

Hans Wey

Walter Wey

Torsten Wey

Carolus Wey

 

Other publications of authors with the same name

Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications., , , and . ICUFN, page 179-181. IEEE, (2019)Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (1): 78-87 (2015)Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (11): 2411-2424 (2009)A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications., , , , and . ISCAS (2), page 1074-1077. IEEE, (2005)From English to ASIC: Hardware Implementation with Large Language Model., , , and . CoRR, (2024)Systolic Array Based Convolutional Neural Network Inference on FPGA., , , and . MCSoC, page 128-133. IEEE, (2022)SF-MMCN: A Low Power Re-configurable Server Flow Convolution Neural Network Accelerator., , and . CoRR, (2024)An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation., , , , , and . ISCAS, page 608-611. IEEE, (2008)Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement., and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 141-153 (2018)Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design., , , , , , and . ISCAS, page 1803-1806. IEEE, (2007)