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Disambiguation of "Riesgo, Teresa"

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Highly Configurable Control Boards: A Tool and a Design Experience.

, , , , and . IEEE International Workshop on Rapid System Prototyping, page 174-. IEEE Computer Society, (2000)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Teresa Edenfeld

Charakterisierung der Funktion der Proteinkinase D2 als Regulator der Chromogranin-A-Sekretion in humanen BON neuroendokrinen Tumorzellen. Uni Ulm, (2010)

Teresa Gaillard

Teresa Krauskopf

Teresa Linares

Teresa Halsband

 

Other publications of authors with the same name

A scalable evolvable hardware processing array., , , , and . ReConFig, page 1-7. IEEE, (2013)Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic., , , and . Microprocess. Microsystems, 38 (8): 899-910 (2014)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework., , , , , and . Sensors, 18 (6): 1877 (2018)Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems., , , and . EURASIP J. Adv. Signal Process., (2011)High-Level Power Analysis for Intellectual Property-Based Digital Systems., and . CSSP, 33 (4): 1035-1051 (2014)Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level., , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 399-408. Springer, (2008)Simulation tool and case study for planning wireless sensor network., , , and . IECON, page 6024-6028. IEEE, (2012)Hardware-software integration platform for a WSN testbed based on cookies nodes., , , and . IECON, page 6013-6018. IEEE, (2012)Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs., , , , , , and . FPL, page 369-375. IEEE Computer Society, (2011)A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays., , , , , and . IPDPS Workshops, page 182-191. IEEE, (2013)