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A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple., , , , , , , and . VLSIC, page 336-. IEEE, (2015)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference., , , , , , , , , and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)Near-threshold operation for power-efficient computing?: it depends..., and . DAC, page 1159-1163. ACM, (2012)Session 12 overview: SRAM., , and . ISSCC, page 204-205. IEEE, (2017)Session 11 overview: Nonvolatile memory solutions., , and . ISSCC, page 194-195. IEEE, (2017)Session 20 overview: Flash-memory solutions: Memory subcommittee., , and . ISSCC, page 334-335. IEEE, (2018)Session 12 overview: DRAM: Memory subcommittee., , and . ISSCC, page 202-203. IEEE, (2018)A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation., , , , , , , , , and 4 other author(s). ISSCC, page 256-258. IEEE, (2011)POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators., , , , and . PACT, page 146-147. IEEE Computer Society, (2017)Across the Stack Opportunities for Deep Learning Acceleration., , , , , , , , , and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)