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Disambiguation of "Bi, Yu"

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Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.

, , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)

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Bi Yu

Yü-Bi Dschou

Hongguang Bi

Bi Wu

Shasha Bi

 

Other publications of authors with the same name

Efficient sensitivity-based capacitance modeling for systematic and random geometric variations., , and . ASP-DAC, page 61-66. IEEE, (2011)Ergodic Channel Capacity of an Amplify-and-Forward Relay System at Low SNR in a Generic Noise Environment., and . IEEE Trans. Signal Process., 60 (5): 2694-2700 (2012)A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios., , , , , , , and . IEEE J. Solid State Circuits, 46 (7): 1585-1595 (2011)Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network., , , and . ASP-DAC, page 493-498. ACM, (2021)HARDeNN: Hardware-assisted attack-resilient deep neural network architectures., , , , and . Microprocess. Microsystems, (November 2022)Reliable and high performance STT-MRAM architectures based on controllable-polarity devices., , , , , and . ICCD, page 343-350. IEEE Computer Society, (2015)Leveraging Emerging Technology for Hardware Security - Case Study on Silicon Nanowire FETs and Graphene SymFETs., , , , , and . ATS, page 342-347. IEEE Computer Society, (2014)Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs., , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)A survey on attack vectors in stack cache memory., , , , , and . Integr., (2020)Robust Self-Learning Physical Layer Abstraction Utilizing Optical Performance Monitoring and Markov Chain Monte Carlo., , , , , , and . ECOC, page 1-3. IEEE, (2017)