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Disambiguation of "Yuan, Jiann-Shiun"

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Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs.

, , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)

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Jiann-Sheng Wu

Jiann-Trzuo Lin

Jiann-Chyuan Lin

Li Yuan

Lei Yuan

 

Other publications of authors with the same name

A scalable and reconfigurable in-memory architecture for ternary deep spiking neural network with ReRAM based neurons., and . Neurocomputing, (2020)Study of performance degradations in DC-DC converter due to hot carrier stress by simulation., , and . Microelectron. Reliab., 46 (9-11): 1840-1843 (2006)NBTI reliability on high-k metal-gate SiGe transistor and circuit performances., , , and . Microelectron. Reliab., 51 (5): 914-918 (2011)Security Protection for Magnetic Tunnel Junction., and . CoRR, (2017)Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs., , , , , and . IEEE Trans. Emerg. Top. Comput., 5 (3): 340-352 (2017)A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs., and . J. Low Power Electron., 13 (3): 497-510 (2017)Analysis and Simulation of Capacitor-Less ReRAM-Based Stochastic Neurons for the in-Memory Spiking Neural Network., and . IEEE Trans. Biomed. Circuits Syst., 12 (5): 1004-1017 (2018)Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design., and . J. Low Power Electron., 2 (2): 201-216 (2006)Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers., and . CDES, page 218-223. CSREA Press, (2005)Low-Side GaN Power Device Dynamic Ron Characteristics Under Different Substrate Biases., , , and . IRPS, page 1-7. IEEE, (2019)