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Optimal scheduling policy for AFDX End-Systems with virtual links of identical bandwidth allocation gap size., , and . CCECE, page 1-4. IEEE, (2012)Multi-processor SoC integration: a case study on BlueGene/L., and . SoCC, page 201-204. IEEE, (2004)An interface for the I2C protocol in the WaferBoard™., , and . ISCAS, page 1492-1495. IEEE, (2013)Mapping applications on two-level configurable hardware., , and . AHS, page 1-8. IEEE, (2015)Modeling the faulty behaviour of digital designs using a feed forward neural network approach., , and . ISCAS, page 1518-1521. IEEE, (2015)Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain., , , and . ISCAS, page 2559-2562. IEEE, (2014)High-voltage operational amplifier based on dual floating-gate transistors., , , and . ISCAS, IEEE, (2006)Spurs modeling in direct digital period synthesizers related to phase accumulator truncation., , and . ISCAS (3), page 389-392. IEEE, (2004)Fast parameters optimization of an iterative decoder using a configurable hardware accelerator., , , , , and . ISCAS (4), page 4159-4162. IEEE, (2005)Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector., and . ISCAS (4), page 369-372. IEEE, (2004)