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Transition time bounded low-power clock tree construction., , and . ISCAS (3), page 2445-2448. IEEE, (2005)FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (5): 722-733 (2005)Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (10): 1652-1663 (2015)Twin binary sequences: a nonredundant representation for general nonslicing floorplan., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 457-469 (2003)FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (1): 70-83 (2008)Area optimization of resilient designs guided by a mixed integer geometric program., , , and . DAC, page 130:1-130:6. ACM, (2016)Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration., , and . DAC, page 42:1-42:6. ACM, (2016)An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations., , and . ASP-DAC, page 361-366. IEEE Computer Society, (2004)FastRoute 2.0: A High-quality and Efficient Global Router., and . ASP-DAC, page 250-255. IEEE Computer Society, (2007)Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design., and . DATE, page 1101. IEEE Computer Society, (2002)