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A Scheduling and Pipelining Algorithm for Hardware/Software Systems., and . ISSS, page 113-. ACM / IEEE Computer Society, (1997)Interactive Ebooks and Course Materials: A BOF for Authors and Instructors (Abstract Only)., , , and . SIGCSE, page 695. ACM, (2015)Model refinement for hardware-software codesign., , and . ACM Trans. Design Autom. Electr. Syst., 2 (1): 22-41 (1997)Model Refinement for Hardware-Software Codesign., , and . ED&TC, page 270-274. IEEE Computer Society, (1996)Clock optimization for high-performance pipelined design., , and . EURO-DAC, page 330-335. IEEE Computer Society Press, (1996)Performance-constrained hierarchical pipelining for behaviors, loops, and operations., and . ACM Trans. Design Autom. Electr. Syst., 6 (1): 1-25 (2001)A memory selection algorithm for high-performance pipelines., and . EURO-DAC, page 124-129. IEEE Computer Society, (1995)Component selection for high-performance pipelines., and . IEEE Trans. Very Large Scale Integr. Syst., 4 (2): 181-194 (1996)Design exploration for high-performance pipelines., and . ICCAD, page 312-316. IEEE Computer Society / ACM, (1994)Top-down modeling of RISC processors in VHDL., , , and . EURO-DAC, page 454-459. IEEE Computer Society, (1993)