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Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding., , , and . ACM Trans. Embed. Comput. Syst., 9 (3): 22:1-22:26 (2010)I/O scheduling with mapping cache awareness for flash based storage systems., , , , and . EMSOFT, page 21:1-21:10. ACM, (2016)Guest Editorial Special Section on Memory Architectures and Organization., and . IEEE Embed. Syst. Lett., 4 (4): 81 (2012)Loop fusion and reordering for register file optimization on stream processors., , , and . J. Syst. Softw., 85 (7): 1673-1681 (2012)Sleep-aware mode assignment in wireless embedded systems., , and . J. Parallel Distributed Comput., 71 (7): 1002-1010 (2011)Optimizing scheduling and intercluster connection for application-specific DSP processors., , , and . IEEE Trans. Signal Process., 57 (11): 4538-4547 (2009)Boosting the Performance of SSDs via Fully Exploiting the Plane Level Parallelism., , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2185-2200 (2020)Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (10): 1660-1673 (2017)Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems., , , , and . IEEE Trans. Computers, 65 (7): 2313-2324 (2016)Online OLED dynamic voltage scaling for video streaming applications on mobile devices., , , and . SIGBED Rev., 10 (2): 18 (2013)