( en | de | ru )

 

Disambiguation of "Lackey, David E."

Author of the publication

copydeleteadd this publication to your clipboard
Design methodology for IBM ASIC products.

, , , , , , , , and . IBM J. Res. Dev., 40 (4): 387-406 (1996)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David E Hopkins

Ursula E E Köhler

Bodo David

Erich David

Ernst David

 

Other publications of authors with the same name

Low cost at-speed testing using On-Product Clock Generation compatible with test compression., , , , , , , , and . ITC, page 724-733. IEEE Computer Society, (2010)Designing mega-ASICs in nanogate technologies., , and . DAC, page 770-775. ACM, (2003)Efficient Latch and Clock Structures for System-on-Chip Test Flexibility.. ITC, page 1-7. IEEE Computer Society, (2006)An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs., , , , , , , , and . VTS, page 173-178. IEEE Computer Society, (2007)Design methodology for IBM ASIC products., , , , , , , , and . IBM J. Res. Dev., 40 (4): 387-406 (1996)Variation-aware performance verification using at-speed structural test and statistical timing., , , , , , and . ICCAD, page 405-412. IEEE Computer Society, (2007)IBM's 50 Million gate ASICs., , and . ASP-DAC, page 628-634. ACM, (2003)The IBM ASIC/SoC methodology - A recipe for first-time success., and . IBM J. Res. Dev., 46 (6): 649-660 (2002)Applying placement-based synthesis for on-time system-on-a-chip design.. CICC, page 121-124. IEEE, (2000)Managing power and performance for System-on-Chip designs using Voltage Islands., , , , , and . ICCAD, page 195-202. ACM / IEEE Computer Society, (2002)