Author of the publication

A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism.

, and . VLSI Design, 15 (2): 521-528 (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A fast, FPGA-based MPEG-2 video encoder with a novel automatic quality control scheme., and . Microprocess. Microsystems, 25 (9-10): 449-457 (2002)A Dynamically Reconfigurable Video Compression Scheme Using FPGAs with Coarse-grain Parallelism., and . VLSI Design, 15 (2): 521-528 (2002)Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization., and . J. Syst. Archit., 51 (6-7): 435-450 (2005)EPLD-based architecture of real time 2D-discrete cosine transform and quantization for image compression., , and . ISCAS (3), page 375-378. IEEE, (1999)Design and implementation of an EPLD-based variable length coder for real time image compression applications., and . ISCAS, page 607-610. IEEE, (2000)Tsallis entropy and particle swarm optimization-based cyclone image vortex localization., , , and . ICACCI, page 235-244. IEEE, (2015)FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression., and . FPGA, page 213-219. ACM, (2001)A Novel, Automatic Quality Control Scheme for Real Time Image Transmission., and . VLSI Design, 14 (4): 329-335 (2002)A programmable pruning level control based MPEG video encoder., and . ISCAS, page 571-574. IEEE, (2000)Parallel Implementation of 2D-Discrete Cosine Transform Using EPLDs., , and . VLSI Design, page 336-339. IEEE Computer Society, (1999)