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DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits.

, , , and . ASYNC, page 73-. IEEE Computer Society, (2000)

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Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy., and . Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, page 13-27. North-Holland, (1993)Modular Timing Constraints for Delay-Insensitive Systems., , , , and . J. Comput. Sci. Technol., 31 (1): 77-106 (2016)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , and . ASYNC, page 60-70. IEEE Computer Society, (1999)Fsimac: a fault simulator for asynchronous sequential circuits., , , , and . Asian Test Symposium, page 114-119. IEEE Computer Society, (2000)Optimal Scan for Pipelined Testing: An Asynchronous Foundation., , and . ITC, page 215-224. IEEE Computer Society, (1996)Low Power and Energy Efficient Asynchronous Design., and . J. Low Power Electron., 3 (3): 234-253 (2007)Mutual Exclusion Sizing for Hoi Polloi., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (6): 1038-1042 (2019)Rob Tristan Gerth: 1956?2003., and . CAV, volume 3114 of Lecture Notes in Computer Science, page 1-14. Springer, (2004)A Framework for Asynchronous Circuit Modeling and Verification in ACL2., , , and . Haifa Verification Conference, volume 10629 of Lecture Notes in Computer Science, page 3-18. Springer, (2017)