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High-Level Debugging and Verification for FPGA-Based Multicore Architectures.

O. Arcas-Abella, A. Cristal, and O. Unsal. FCCM, page 135-142. IEEE Computer Society, (2015)

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Adrián Juárez

Adrián Granada

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

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EVX: Vector execution on low power EDGE cores.M. Duric, O. Palomar, A. Smith, O. Unsal, A. Cristal, M. Valero, and D. Burger. DATE, page 1-4. European Design and Automation Association, (2014)A Deep Learning Mapper (DLM) for Scheduling on Heterogeneous Systems.D. Nemirovsky, T. Arkose, N. Markovic, M. Nemirovsky, O. Unsal, A. Cristal, and M. Valero. CARLA, volume 796 of Communications in Computer and Information Science, page 3-20. Springer, (2017)VALib and SimpleVector: tools for rapid initial research on vector architectures.M. Stanic, O. Palomar, I. Ratkovic, M. Duric, O. Unsal, and A. Cristal. Conf. Computing Frontiers, page 7:1-7:10. ACM, (2014)Stand-Alone Memory Controller for Graphics System.T. Hussain, O. Palomar, O. Ünsal, A. Cristal, E. Ayguadé, M. Valero, and A. Haider. ARC, volume 8405 of Lecture Notes in Computer Science, page 108-120. Springer, (2014)RMS-TM: a comprehensive benchmark suite for transactional memory systems.G. Kestor, V. Karakostas, O. Unsal, A. Cristal, I. Hur, and M. Valero. ICPE, page 335-346. ACM, (2011)On the selection of adder unit in energy efficient vector processing.I. Ratkovic, O. Palomar, M. Stanic, O. Unsal, A. Cristal, and M. Valero. ISQED, page 143-150. IEEE, (2013)Transactional Memory: An Overview.T. Harris, A. Cristal, O. Unsal, E. Ayguadé, F. Gagliardi, B. Smith, and M. Valero. IEEE Micro, 27 (3): 8-29 (2007)The Velox Transactional Memory Stack.Y. Afek, U. Drepper, P. Felber, C. Fetzer, V. Gramoli, M. Hohmuth, E. Rivière, P. Stenström, O. Unsal, W. Maldonado and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)Dynamic transaction coalescing.S. Stipic, V. Karakostas, V. Smiljkovic, V. Gajinov, O. Unsal, A. Cristal, and M. Valero. Conf. Computing Frontiers, page 18:1-18:10. ACM, (2014)AMMC: Advanced Multi-Core Memory Controller.T. Hussain, O. Palomar, O. Unsal, A. Cristal, E. Ayguadé, M. Valero, and S. Gursal. FPT, page 292-295. IEEE, (2014)

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Disambiguation of "Cristal, Adrián"

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High-Level Debugging and Verification for FPGA-Based Multicore Architectures.

Please choose a person to relate this publication to

Adrián Juárez

Adrián Granada

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Cristal, Adrián"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML High-Level Debugging and Verification for FPGA-Based Multicore Architectures.

Please choose a person to relate this publication to

Adrián Juárez

Adrián Granada

Adrián Navigante

Adrián Vergara Durán

Adrián Cartín-Valverde

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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High-Level Debugging and Verification for FPGA-Based Multicore Architectures.