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pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems.

, , , , , and . DSD, page 404-412. IEEE Computer Society, (2016)

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Predictable performance in SMT processors., , , , , and . Conf. Computing Frontiers, page 433-443. ACM, (2004)High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V., , , and . IEEE Micro, 38 (1): 56-65 (2018)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems., , , , and . RTAS, page 267-278. IEEE Computer Society, (2016)Resilient random modulo cache memories for probabilistically-analyzable real-time systems., , , and . IOLTS, page 27-32. IEEE, (2016)Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore., , , , , and . SAFECOMP Workshops, volume 9923 of Lecture Notes in Computer Science, page 273-285. Springer, (2016)Achieving timing composability with measurement-based probabilistic timing analysis., , , , and . ISORC, page 1-8. IEEE Computer Society, (2013)Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors., , , , , , and . ISORC, page 208-217. IEEE Computer Society, (2015)Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns., , and . ISORC, page 142-149. IEEE Computer Society, (2016)MLP-Aware Dynamic Cache Partitioning., , , and . PACT, page 418. IEEE Computer Society, (2007)