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Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Reducing the data switching activity of serialized datastreams., , , and . ISCAS, IEEE, (2006)Session 2 overview: Processors: Digital architectures and systems subcommittee., , and . ISSCC, page 32-33. IEEE, (2018)A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS., , , , , , and . IEEE J. Solid State Circuits, 49 (4): 917-927 (2014)Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays., , and . VLSI Design, 4 (4): 275-291 (1996)Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)Design for test and reliability in ultimate CMOS., , , , , , , , , and 4 other author(s). DATE, page 677-682. IEEE, (2012)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS., , , , , , and . ISSCC, page 380-382. IEEE, (2020)A Low-Power High-Performance Embedded SRAM Macrocell., , and . Great Lakes Symposium on VLSI, page 13-17. IEEE Computer Society, (1998)Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS., , , , and . CICC, page 1-4. IEEE, (2015)