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Enforcing Predictability of Many-Cores With DCFNoC., , , and . IEEE Trans. Computers, 70 (2): 270-283 (2021)SafeSU-2: a Safe Statistics Unit for Space MPSoCs., , , , , , and . DATE, page 1085-1086. IEEE, (2022)A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors., , , , , , , , , and 10 other author(s). ETS, page 1-10. IEEE, (2023)HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem., , , , and . FPL, page 52-59. IEEE, (2021)Locality-aware cache random replacement policies., , , and . J. Syst. Archit., (2019)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems., , , , and . RTAS, page 267-278. IEEE Computer Society, (2016)Random modulo: a new processor cache design for real-time critical systems., , , , and . DAC, page 29:1-29:6. ACM, (2016)Design and implementation of a fair credit-based bandwidth sharing scheme for buses., , , and . DATE, page 926-929. IEEE, (2017)Design and integration of hierarchical-placement multi-level caches for real-time systems., , , and . DATE, page 455-460. IEEE, (2018)High-Integrity GPU Designs for Critical Real-Time Automotive Systems., , , and . DATE, page 824-829. IEEE, (2019)