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A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 47 (12): 3184-3196 (2012)A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique., , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1721-1729 (2013)Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS., , , , , and . ISCAS, page 1-4. IEEE, (2020)A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC., , , , , , and . ESSCIRC, page 193-196. IEEE, (2012)A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS., , , , , , , , , and 5 other author(s). VLSIC, page 76-77. IEEE, (2012)A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs., and . CICC, page 263-266. IEEE, (2009)A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O., , , , and . ISLPED, page 1-6. IEEE, (2017)A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 168-170. IEEE, (2012)A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 57-II (8): 602-606 (2010)A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management., , , , and . ISSCC, page 352-354. IEEE, (2012)