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A Compact DSP Core with Static Floating-Point Arithmetic., , , , and . VLSI Signal Processing, 42 (2): 127-138 (2006)Improving datapathutilization of programmable DSP with composite functional units., , , and . ISCAS, page 3438-3441. IEEE, (2008)An ultra-low voltage hearing aid chip using variable-latency design technique., , , , , and . ISCAS, page 2543-2546. IEEE, (2014)Pipelining technique for energy-aware datapaths., , , , and . ISCAS (2), page 1218-1221. IEEE, (2005)A 52mW 1200MIPS compact DSP for multi-core media SoC., , , , , , and . ASP-DAC, page 118-119. IEEE, (2006)What consumers see when time is running out: Consumers' browsing behaviors on online shopping websites when under time pressure., , , and . Comput. Hum. Behav., (2017)Parallelizing Complex Streaming Applications on Distributed Scratchpad Memory Multicore Architecture., , , and . Int. J. Parallel Program., 42 (6): 875-899 (2014)Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (10): 2631-2643 (2013)Phase sequence interchange scheme for suppressing transient cross regulation on the compensator controlled and non-compensator controlled single-inductor dual-output buck converter., , , , and . IET Circuits Devices Syst., 15 (7): 657-669 (2021)A Low Latency NN-Based Cyclic Jacobi EVD Processor for DOA Estimation in Radar System., , and . ISCAS, page 1-5. IEEE, (2020)