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A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic.

, , , and . Asian Test Symposium, page 90-95. IEEE Computer Society, (2003)

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Khulna-9208, Bangladesh** Department of Computer Science, University of Dhaka Dhaka-1000, Bangladesh, , , and . Proceedings, International Conference on Computer and Information Technology, December 28-29, 2001, 32, page 62. Department of Computer Science, University of Dhaka, (2001)An efficient design technique of a quantum divider circuit., , and . ISCAS, page 2102-2105. IEEE, (2016)An efficient approach for designing and minimizing reversible programmable logic arrays., , , and . ACM Great Lakes Symposium on VLSI, page 215-220. ACM, (2012)An efficient approach to design a reversible control unit of a processor., , and . Sustain. Comput. Informatics Syst., 3 (4): 286-294 (2013)Efficient Techniques for Fault Detection and Correction of Reversible Circuits., , and . J. Electron. Test., 33 (5): 591-605 (2017)A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design., , , and . CoRR, (2022)Synthesis of Full-Adder Circuit Using Reversible Logic., , , and . VLSI Design, page 757-760. IEEE Computer Society, (2004)Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder., and . VLSI Design, page 255-260. IEEE Computer Society, (2005)An Efficient Design of a Reversible Barrel Shifter., and . VLSI Design, page 93-98. IEEE Computer Society, (2010)A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic., , , and . Asian Test Symposium, page 90-95. IEEE Computer Society, (2003)