( en | de | ru )

 

Disambiguation of "Keane, John"

Author of the publication

copydeleteadd this publication to your clipboard
Effect of Road Surface, Vehicle, and Device Characteristics on Energy Harvesting from Bridge-Vehicle Interactions.

, , , , , , and . Comput. Aided Civ. Infrastructure Eng., 31 (12): 921-935 (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Michael Keane

Horst John

Annemarie Johne

Hans-Dieter John

Walter John

 

Other publications of authors with the same name

On-chip reliability monitors for measuring circuit degradation., , , and . Microelectron. Reliab., 50 (8): 1039-1053 (2010)An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (6): 947-956 (2010)A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing., , , and . IEEE J. Solid State Circuits, 43 (2): 518-529 (2008)A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (1): 222-229 (2016)5.6 Mb/mm2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology., , , , , , and . IEEE J. Solid State Circuits, 52 (1): 229-239 (2017)An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB., , , and . IEEE J. Solid State Circuits, 45 (4): 817-829 (2010)An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs., , and . ESSDERC, page 262-265. IEEE, (2012)Modeling and analysis of leakage induced damping effect in low voltage LSIs., , and . ISLPED, page 382-387. ACM, (2006)An array-based test circuit for fully automated gate dielectric breakdown characterization., , , and . CICC, page 121-124. IEEE, (2008)Circuit techniques for ultra-low power subthreshold SRAMs., , , and . ISCAS, page 2574-2577. IEEE, (2008)