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Disambiguation of "Fujiwara, Hideo"

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Enabling False Path Identification from RTL for Reducing Design and Test Futileness.

, , and . DELTA, page 20-25. IEEE Computer Society, (2010)

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Esther Fujiwara

Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

The Complexity of Fault Detection Problems for Combinational Logic Circuits., and . IEEE Trans. Computers, 31 (6): 555-560 (1982)A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings., , , and . J. Parallel Distributed Comput., 62 (5): 865-884 (2002)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)System-on-chip test scheduling with reconfigurable core wrappers., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Effect of BIST Pretest on IC Defect Level., , and . IEICE Trans. Inf. Syst., 89-D (10): 2626-2636 (2006)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , and . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , and . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , and . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., and . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , and . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)