Author of the publication

A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion.

, , and . IEEE J. Solid State Circuits, 50 (12): 2988-3002 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (9): 2259-2268 (2010)Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 965-974 (2021)A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2013-2023 (2015)A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation., , , , and . IEEE J. Solid State Circuits, 45 (12): 2723-2736 (2010)A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques., , , , and . IEEE J. Solid State Circuits, 44 (3): 824-834 (2009)Insights into wideband fractional All-Digital PLLs for RF applications., , , , and . CICC, page 37-44. IEEE, (2009)GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity., , , and . ISSCC, page 232-234. IEEE, (2011)Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation., , , and . IEEE J. Solid State Circuits, 47 (9): 2164-2173 (2012)Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement., and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 1-19 (2019)A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction., , , and . ISSCC, page 344-345. IEEE, (2008)