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Disambiguation of "Yamaguchi, Hisakatsu"

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F3: Emerging technologies for wireline communication.

, , , , , , and . ISSCC, page 504-505. IEEE, (2013)

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Shigeo Yamaguchi

Fabian Yamaguchi

Ichiro Yamaguchi

Ichiro Yamaguchi

Yoko Yamaguchi

 

Other publications of authors with the same name

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs., , , , and . IEEE J. Solid State Circuits, 53 (9): 2696-2708 (2018)A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 978-985 (2005)18-GHz Clock Distribution Using a Coupled VCO Array., , , , , and . IEICE Trans. Electron., 90-C (4): 811-822 (2007)F6: Energy-efficient I/O design for next-generation systems., , , , , and . ISSCC, page 520-521. IEEE, (2014)Training Deep Neural Networks in 8-bit Fixed Point with Dynamic Shared Exponent Management., , , and . DATE, page 1536-1541. IEEE, (2021)On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR., , , and . IEEE J. Solid State Circuits, 53 (3): 750-761 (2018)A CMOS multichannel 10-Gb/s transceiver., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 38 (12): 2094-2100 (2003)A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution., , , , , , , , , and 6 other author(s). VLSIC, page 1-2. IEEE, (2014)A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS., , , , , , , , , and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS., , , , , , and . ISSCC, page 166-167. IEEE, (2010)