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The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 53 (1): 91-101 (2018)Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability., , , , , and . Microelectron. Reliab., 49 (6): 642-649 (2009)Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (11): 3057-3066 (2017)SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage., , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 24-32 (2011)POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology., , , , , , , , , and 2 other author(s). ISSCC, page 48-50. IEEE, (2022)Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis., , , , , , , , and . ICCAD, page 458-465. IEEE, (2013)Variations: Sources and Characterization., and . Low-Power Variation-Tolerant Design in Nanometer Silicon, Springer, (2011)Efficient techniques for gate leakage estimation., , , and . ISLPED, page 100-103. ACM, (2003)IBM POWER9 circuit design and energy optimization for 14-nm technology., , , , and . IBM J. Res. Dev., 62 (4/5): 4:1-4:11 (2018)IBM POWER8 circuit design and energy optimization., , , , , , , , , and 13 other author(s). IBM J. Res. Dev., (2015)