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IBM POWER8 circuit design and energy optimization.

V. Zyuban, J. Friedrich, D. Dreps, J. Pille, D. Plass, P. Restle, Z. Deniz, M. Ziegler, S. Chu, M. Islam, J. Warnock, B. Philhower, R. Rao, G. Still, D. Shan, E. Fluhr, J. Paredes, D. Wendel, C. Gonzalez, D. Hogenmiller, R. Puri, S. Taylor, and S. Posluszny. IBM J. Res. Dev., (2015)

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Ufuk Toprak

Hanefi Toprak

Cengiz Deniz

Vedat Deniz

Abdülkerim Deniz

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A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.J. Proesel, Z. Deniz, A. Cevrero, I. Özkaya, S. Kim, D. Kuchta, S. Lee, S. Rylov, H. Ainspan, T. Dickson and 2 other author(s). IEEE J. Solid State Circuits, 53 (4): 1214-1226 (2018)A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration.T. Dickson, Y. Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Beakes, M. Meghelli, and D. Friedman. IEEE J. Solid State Circuits, 51 (8): 1744-1755 (2016)A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS.Z. Deniz, J. Proesel, J. Bulzacchelli, H. Ainspan, T. Dickson, M. Beakes, and M. Meghelli. IEEE J. Solid State Circuits, 55 (1): 19-26 (2020)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS.M. Perez, M. Sperling, J. Bulzacchelli, Z. Deniz, and T. Diemoz. IEEE J. Solid State Circuits, 55 (3): 731-743 (2020)On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation.Z. Deniz, Y. Leblebici, and E. Vittoz. IEEE J. Solid State Circuits, 42 (7): 1593-1606 (2007)Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS.M. Perez, M. Sperling, T. Diemoz, J. Bulzacchelli, and Z. Deniz. CICC, page 1-4. IEEE, (2019)Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.Z. Deniz, Y. Leblebici, and E. Vittoz. VLSI-SoC (Selected Papers), volume 249 of IFIP, page 217-240. Springer, (2006)Low-power current mode logic for improved DPA-resistance in embedded systems.Z. Deniz, and Y. Leblebici. ISCAS (2), page 1059-1062. IEEE, (2005)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.T. Dickson, Y. Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, and D. Friedman. CICC, page 1-4. IEEE, (2015)Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications.A. Rylyakov, J. Tierno, H. Ainspan, J. Plouchart, J. Bulzacchelli, Z. Deniz, and D. Friedman. ISSCC, page 94-95. IEEE, (2009)

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Disambiguation of "Deniz, Zeynep Toprak"

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IBM POWER8 circuit design and energy optimization.

Please choose a person to relate this publication to

Ufuk Toprak

Hanefi Toprak

Cengiz Deniz

Vedat Deniz

Abdülkerim Deniz

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Deniz, Zeynep Toprak"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML IBM POWER8 circuit design and energy optimization.

Please choose a person to relate this publication to

Ufuk Toprak

Hanefi Toprak

Cengiz Deniz

Vedat Deniz

Abdülkerim Deniz

Other publications of authors with the same name

Disambiguation

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URL
DOI
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IBM POWER8 circuit design and energy optimization.